US20240169240
2024-05-23
Physics
G06N10/40
A fault-tolerant quantum computer utilizes topological codes, specifically surface codes, to minimize idle volume. The architecture comprises qubit modules that generate surface code patches for various qubits, interconnected through a network that includes specialized connections. These connections facilitate the coupling of surface code patch boundaries and enable the transfer of surface code states between qubit modules.
The system features two main types of connections: "port" connections and "quickswap" connections. Port connections allow for the selective coupling of boundaries between surface code patches across different qubit modules within a defined range. Quickswap connections enable the direct transfer of the state of a surface code patch from one qubit module to another, forming a log-tree network that enhances connectivity among qubits.
Each qubit module is equipped with circuitry to operate on multiple physical qubits, generating topological code patches for logical qubits during several code cycles. The quickswap connections are designed to facilitate state swapping between pairs of qubit modules efficiently, even when they are not physically adjacent. This configuration allows for complex operations to occur within a single code cycle.
The system incorporates classical control logic circuitry that manages the operation of quickswap connections, enabling or disabling them as necessary. The architecture supports concurrent quickswap operations for multiple disjoint pairs of qubit modules, optimizing performance and resource utilization during quantum computations.
A method is outlined for executing logical cycles consisting of multiple code cycles. This involves storing logical qubits in memory modules and performing quickswap operations with workspace modules to facilitate logical gate operations. The iterative process rearranges logical qubits in memory in preparation for subsequent cycles, enhancing the overall efficiency and fault tolerance of the quantum computing system.