Complementary 2(N)-bit redundancy for single event upset prevention

Smart overview of the Invention

Single event upsets (SEUs) pose significant risks to integrated circuits, particularly when exposed to environmental conditions like solar radiation. Charged particles can cause voltage spikes, leading to errors in logic elements, which may alter intended data values. Such vulnerabilities can severely impact the functionality of critical systems such as medical devices, satellites, and voting machines, underscoring the need for effective SEU prevention strategies.

Limitations of Existing Techniques

Traditional methods for mitigating SEUs often rely on hardware redundancy, such as triple modular redundancy (TMR). While these approaches aim to create distance between redundant elements to minimize risk, they do not effectively address vulnerabilities to intentional attacks. An attacker aware of the redundancy configuration can exploit identical elements, rendering these techniques insufficient against deliberate threats or certain types of single event transients.

Complementary 2(N)-Bit Redundancy

The proposed complementary 2(N)-bit redundancy approach introduces a novel architecture for integrated circuits designed to prevent SEUs. This system incorporates multiple data storage elements that store both original and complementary values. By employing this dual storage strategy, the circuit minimizes the risk of simultaneous errors affecting both data states, thereby enhancing resilience against both accidental and intentional disruptions.

Circuit Configuration

An integrated circuit implementing this redundancy features an input node for receiving data values and two distinct storage elements: one for the original value and another for the complementary value. Additionally, a multi-bit storage element retains both values separately. The circuit is equipped with voting logic that processes inputs from these storage elements, ensuring that the output reflects the most reliable data by assessing multiple logic values to determine the correct state.

Error Detection and Dynamic Adaptation

The integrated circuit's voting logic not only facilitates error detection but also allows for dynamic programming based on detected SEU failures. This adaptability enables the system to respond effectively to varying conditions and threats, making it a robust solution for safeguarding critical electronic devices from SEUs and related errors. Through this innovative design, complementary 2(N)-bit redundancy significantly enhances data integrity in vulnerable environments.