US20250265206
2025-08-21
Physics
G06F13/1668
The memory system described involves a memory controller and a memory device that communicate via a data input/output signal. This system uses a combination of pulse amplitude modulation (PAM)-N mode and non-return to zero (NRZ) mode to enhance the efficiency of data transmission. The system is designed to handle commands, addresses, and data over a first channel with differing voltage levels, optimizing the interface between the memory controller and the memory device.
The invention is related to memory devices, focusing on improving input/output interfaces for systems such as solid-state drives (SSDs). These devices require efficient data handling due to their quick access times and low latency. The interface efficiency is critical for managing the transmission time of commands, addresses, and data between the memory controller and memory device.
The system utilizes a dual-mode signaling method. During a first time interval, the memory controller sends signals with one of N different voltage levels using PAM-N mode. In the second time interval, it switches to NRZ mode with two voltage levels. The memory device samples these signals accordingly, allowing for flexible and efficient data processing.
The described system includes multiple channels connecting a memory controller to various memory devices. Each channel can handle different commands, addresses, and data simultaneously. This parallel processing capability allows for improved performance in data handling and storage operations.
The memory controller manages the overall operation by selecting specific memory devices connected via channels, transmitting necessary commands and data. It controls each device individually while supporting parallel signal transmission across different channels. This setup enhances the speed and efficiency of data processing within the memory system.