THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Smart overview of the Invention

The patent application describes a three-dimensional semiconductor device comprising multiple active regions and channel patterns. These components are arranged in a vertically stacked configuration on a substrate, with the first active region directly on the substrate and subsequent regions stacked above it. A key feature is the inclusion of ferroelectric patterns that enhance the device's reliability and performance by being strategically placed between various semiconductor patterns and source/drain patterns.

Design and Structure

The device includes a first active region with a first channel pattern and source/drain patterns, connected through this channel. Above this, a second active region is stacked, also containing a channel pattern and source/drain patterns. A gate electrode is positioned over these channel patterns, facilitating control over the transistor operations. The channel patterns are characterized by their composition of multiple semiconductor patterns, spaced vertically to optimize performance.

Ferroelectric Integration

A notable aspect of the design is the integration of ferroelectric patterns between certain layers. Specifically, a first ferroelectric pattern is placed between the substrate and the first semiconductor pattern, enhancing the electrical characteristics of the device. This pattern is crucial in stabilizing the operation of the semiconductor components, contributing to improved reliability and efficiency.

Fabrication Methodology

The method of fabricating this semiconductor device involves sequential stacking of active regions over an insulating layer on the substrate. Each active region serves as either a p-type or n-type MOSFET region, contributing to a three-dimensional stack transistor configuration. The process aims to achieve precise alignment and spacing of semiconductor patterns to maintain operational integrity and meet scaling demands.

Technical Challenges Addressed

The invention addresses limitations associated with scaling down MOSFETs in semiconductor devices. By implementing a three-dimensional structure with integrated ferroelectric materials, the design mitigates performance deterioration typically observed in smaller devices. This approach enables the realization of high-performance, reliable semiconductor devices suitable for advanced technological applications.