US20260096138
2026-04-02
Electricity
H10D30/6706
The semiconductor device described includes a channel made from a two-dimensional semiconductor material, which is flanked by a source electrode and a drain electrode. Above this channel, several layers are sequentially deposited: a two-dimensional material oxide layer, a dipole oxide layer, a dielectric layer, and finally, a gate electrode. These layers, particularly the dipole oxide and dielectric layers, are designed to allow for an adjustable threshold voltage, which is crucial for the device's operation in various electronic applications.
The dipole oxide layer can be composed of materials such as La2O3, Al2O3, ScO, Y2O3, or MgO, while the dielectric layer may include HfO2, ZrO2, or HfZrO. The channel itself may be formed from materials like transition metal dichalcogenides (TMD), graphene, black phosphorus, or phosphorene. The TMD materials can include metal elements such as Mo, W, Nb, and others, combined with chalcogen elements like S, Se, and Te.
The thickness of the two-dimensional material oxide layer ranges from greater than 0 nm to about 2 nm, while the dipole oxide layer shares a similar thickness range. The dielectric layer is slightly thicker, with a range extending up to about 5 nm. These layers are configured to surround the channel, with the gate electrode encompassing the entire assembly, ensuring effective electrical control over the channel.
The manufacturing process involves creating a stack structure by alternately forming a dummy layer and a channel on a substrate. After establishing the source and drain electrodes, the dummy layer is removed, and the subsequent layers are deposited in sequence: the two-dimensional material oxide layer, dipole oxide layer, dielectric layer, and finally, the gate electrode. This method ensures precise layer formation and integration into electronic devices.
This semiconductor device can be integrated into a variety of electronic apparatuses, enhancing their functionality with adjustable threshold voltages. The described structure and materials allow for high integration levels in circuits, making them suitable for use in memory devices, logic devices, and other integrated circuits. The described method and materials support advancements in miniaturization and performance enhancement of semiconductor technologies.