US20260143737
2026-05-21
Electricity
H10D30/481
The patent application discusses a semiconductor device featuring a substrate, a source electrode, and a drain electrode with a channel in between. This channel comprises a two-dimensional material, which connects the source to the drain electrode. A gate insulating layer is positioned on the channel, and a gate electrode is placed on the insulating layer. Notably, the gate electrode has an overlap area facing the source electrode vertically, enhancing the device's performance by reducing contact resistance.
Semiconductors, specifically transistors, are crucial in integrated circuit devices like memories and logic devices. As the demand for higher integration increases, the size of transistors has been reduced. This miniaturization poses challenges such as short channel effects, which include threshold voltage variation and carrier velocity saturation. The invention addresses these issues by optimizing the contact area between the gate electrode and the channel, thereby improving power efficiency.
The semiconductor device utilizes a two-dimensional material for the channel, which could be made from materials like transition metal dichalcogenide (TMD), graphene, or phosphorene. The gate insulating layer may consist of high-k or ferroelectric materials. Additionally, the device includes multiple channel layers, separated by spacers, which are strategically positioned to enhance performance. The spacer's thickness varies, with the one adjacent to the source electrode being thinner than the one next to the drain electrode.
The manufacturing method involves stacking a sacrificial layer and a channel on a substrate, followed by patterning and forming source and drain electrodes. The sacrificial layer is then removed to suspend the channel. Spacers are placed between channel layers, with a gate insulating layer and gate electrode subsequently deposited. The method ensures that the first spacer is thinner than the second, optimizing the device's electrical characteristics.
This semiconductor device and its manufacturing method present advancements in reducing contact resistance and managing leakage currents effectively. By using two-dimensional materials and strategically designed components like asymmetrical gate electrodes and varying spacer thicknesses, the invention aims to overcome the limitations of miniaturized transistors, such as short channel effects, thereby enhancing the efficiency and performance of integrated circuits.