NPN CANONIZATION OF BOOLEAN FUNCTIONS

Smart overview of the Invention

The patent application discusses a method for optimizing Boolean functions through a process known as Negation-Permutation-Negation (NPN) canonization. This technique is crucial in the realm of integrated circuit design, where Boolean logic forms the foundation of digital circuits. The process involves transforming Boolean functions into a standardized form to enhance logic synthesis and functional verification.

Methodology

The technique is implemented via a computer program or data processing system. Initially, an input Boolean function with multiple variables is received. These variables are systematically ordered to create variable partitions. The core of the method is the search for the NPN canonical form, which is efficiently executed by dynamically constraining the search space through symmetry groups within the partitions. The resulting canonical form is then stored for further use.

Processing Details

The ordering of variables is crucial and involves resolving ties using coefficients for complement sets and impact function values when traditional metrics like Hadamard-Walsh coefficients fall short. This ordered partitioning aids in the efficient search for the NPN canonical form, reducing computational resources and time. The method also includes refining these partitions to expedite the search process.

Application in Circuit Design

Once the NPN canonical form is identified, it can replace the original Boolean function in digital circuit designs. This transformation is beneficial during logical verification and logic synthesis stages of electronic design automation (EDA). The use of NPN canonical forms accelerates these processes, optimizes circuit performance, and minimizes design errors.

Implementation and Benefits

The method can be embodied in a computer program product, where the program code executes the described operations. By efficiently limiting the search space and utilizing ordered variable partitions, the approach significantly accelerates the processing of Boolean functions in integrated circuit design. This results in resource-efficient processing, enhancing overall design performance and reliability.